1. Technical Field
The present invention relates to a method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving system resistance and characteristic impedance requirements.
2. Related Art
Semiconductor chip size continues to decrease, with an attendant increase in component density. The electrical signals which provide communication between chips, via electrically conductive wires or lines, are characterized by increasing operational frequencies. Semiconductor chips mounted on a printed circuit board (xe2x80x9cPCBxe2x80x9d) are subjected to detrimental effects caused by the inherent resistance of the PCB wiring which interconnects the semiconductor chips. A typical high performance printed circuit board has traditionally not been able to use wiring densities beyond a certain point due to limitations imposed by the DC resistance maximum in interchip wiring networks. Similarly, higher frequency signals also demand wide lines as a means to minimize xe2x80x9cskin effectxe2x80x9d losses in long lines. Unfortunately, it is problematic to generate dense wiring between a plurality of semiconductor chips on a PCB or chip carrier.
The usual solution is to use the typical geometry of wide wire lines and appropriate dielectric layer thicknesses to produce a 50 ohm transmission line characteristic impedance (Z0), and achieve a wiring network with a single wiring layer pair that uses only lower capacitance buried vias and a limited number of higher capacitance plated through hole vias. The result of this approach is that more wiring layers are required, and with a correspondingly thicker printed circuit board structure resulting. Future projections of component input/output (I/O) counts (e.g., approaching 4000 I/O counts with an I/O pitch of 0.8 mm) require a solution other than this usual practice.
An alternative is to use fine wire lines that widen when sufficient space is available. However, these wire lines do not maintain the necessary transmission line characteristic impedance (Z0) in all areas. These wire lines also have circuitization yield implications that make them unattractive in most printed circuit board applications.
Thus, there is a need for a method and structure that implements dense wiring, in printed circuit board or chip carrier applications, and which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements.
The present invention discloses a structure and associated method of implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements.
In addition, the present invention provides reduced thickness printed circuit boards by providing selective dense wiring layers, and enables dense designs that were heretofore difficult to wire.
The present invention provides a multilayered circuit board assembly comprising: a first wiring layer having at least one first conductor, each first conductor having a first cross-sectional area; a second wiring layer having at least one second conductor, the second conductor having a cross-sectional area smaller than a cross-sectional area of said first conductor; said multilayered circuit board assembly having a first area of high component density and a second area of lower component density; said first area of high component density connected to said at least one second conductor.
The present invention further provides a method of increasing circuit wiring density in a printed circuit board while maintaining an impedance level and reducing electrical noise, said method comprising: providing a first wiring layer containing at least one first wire type having a first impedance, said first wiring layer having a first conductor; providing a second wiring layer containing at least one second wire type having a second impedance, said second wiring layer having a second conductor; wherein the impedance of said first wire type is equal to the impedance of said second wire type; and wherein said first wire type is used to produce said first conductor, and said second wire type is used to produce said second conductor.
The present invention also provides a multilayered circuit board assembly having a plurality of networks, said multilayered circuit board comprising: a first wiring layer having at least one first conductor, the first conductor having a first cross-sectional area; a second wiring layer having at least one second conductor, the second conductor having a second cross-sectional area, said second cross-sectional area being smaller than said first cross-sectional area; said multilayered circuit board having a maximum wire resistance limit; and said second wiring layer having electrical connections to networks such that the total resistance of the network connections remains within a maximum wire resistance limit.
The present invention additionally provides a method of maintaining a characteristic impedance level in wires of a printed circuit board, said method comprising: providing a first wiring layer containing at least one first wire of a first type, wherein said first wire has a first cross-sectional area; providing a second wiring layer containing at least one second wire of a second type, wherein said second wire has a second cross-sectional area; wherein said first cross-sectional sectional area is not equivalent to said second cross-sectional area; and wherein said first wire and said second wire have the same electrical characteristic impedance.
The present invention therefore provides a method and structure that implements dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics, while preserving the system resistance and characteristic impedance requirements.